tech

State-of-the-art lithography for creating smaller features is increasingly being supplemented by improvements in lithography through mature process nodes, as both are required for the integration of System on Chips (SoCs) and complex chips that are broken down and integrated into advanced packaging.

Before the era of 7nm, the main goal of leading chip manufacturers was to encapsulate everything into a single System on Chip (SoC) using the same process technology. Since then, these chips have increasingly been divided into separate chips, chipslets, or modules, allowing chip manufacturers to add many new features that were previously shelved due to the limited EUV mask area (858 square millimeters). This division also allows chip manufacturers to retain analog functions such as RF and power in any process technology that makes the most sense, without incurring the high cost and hassle of creating a main digital function with analog components (commonly referred to as Big D/Small A).

Advertisement

Intel Foundry Services, Samsung Foundry, and TSMC continue to support ASML in developing more advanced lithography equipment—each new High NA EUV lithography machine is reportedly priced at $340 million, and hyper-NA EUV also appears in some future node roadmaps. But the more pressing issue is how to scale 193-nanometer immersion technology, which GlobalFoundries estimates accounts for 80% of all semiconductors. Everything from electric vehicles and charging stations to medical devices, and even less critical functions in servers, requires these chips.

"You will optimize any lithography technology you have," said Harry Levinson, Chief Lithographer at HJL Lithography.

There are now two things at play, and they are related. One is inverse lithography technology, which allows you to maximize the process window, so you can squeeze a little more out of any given wavelength from any given optical system. This has been hindered by computational speed in the past, as applying it to a complete chip was too slow, and even for small parts of the circuit, it was almost impractical. But it is accelerating, and people have already applied it to larger and larger parts of their layouts. We are ready to be able to apply it to the entire chip. At least one company (Micron) has submitted a paper saying they are doing this.

Related to this is the ability to print curved features instead of straight-line features. "The process window is better with curved features compared to straight-line approximations," Levinson said. "There are many obstacles, and people are working hard to address these issues. But the use of curved features was one of the biggest topics at the recent Photomask Japan [2023] conference, and it is definitely a theme at the [SPIE] Advanced Lithography and Patterning in February."

While the need to shrink some digital logic to below the 1nm range using High NA EUV will continue, there is a simultaneous explosive growth in the 193nm deep ultraviolet (DUV) range, which is where many chips and analog functions are being developed.

A good measure of 193nm activity is 200mm wafer capacity. Clark Tseng, Senior Director of SEMI Market Intelligence, estimates that global capacity will grow from 6.9 million wafers per month in 2023 to 7.5 million in 2026, an increase of 8.7%. He notes that, at least for now, the role of traditional 200mm processes in chiplet architectures is limited.

The chiplets used today are limited to the largest chip manufacturers, and almost all of these chiplets are internally developed. But as chiplets become commercialized, this will change over time, and the demand for DUV capacity may grow.

"The demand for high-level mixing and matching of functions is exceptionally strong, so you don't have to redesign each custom chip for every market segment," said Mike Kelly, Vice President of Advanced Packaging Development and Technology Integration at Amkor Technology. "It becomes feasible and cost-effective, and you will see system architects really starting to take advantage of it. As we demonstrate more and more that things are ready for prime time, these architectures will say—okay, great, I can do that. This is relatively risk-free. Now, how about this?"There are many ways to design a system on a chip, or a system composed of chips or chips in advanced packaging. Unless the form factor dictates that everything needs to be squeezed into the smallest possible area, in many cases, a collection of chips or chips developed on a mature node with DUV and using high-speed interface packaging may be sufficient, and the cost is much lower.

GlobalFoundries Chief Technology Officer Gregg Bartlett said in an interview last year: "Our 22FDX is an epiphany." "It's like a Swiss Army knife. It can achieve ultra-low leakage. You can achieve ultra-low power consumption. You can do millimeter waves. You can apply high voltage on it because you can build devices in batches with SOI devices, of course, you can speed up the time to market for any product that customers want."

The number of choices is increasing, from different materials and architectures, to different ways of using existing technologies. Given the industry's familiarity with double patterning, most of which is due to the repeated delays in bringing EUV to the market, 193nm lithography technology has been widely proven to be as low as 14nm.

"Although all the top talents of EUV fabs are working on EUV, most fabs usually don't have it—and don't plan to have it," said Aki Fujimura, CEO of D2S. "Therefore, the industry has a lot of top talents who have time to study non-EUV cutting-edge technologies and continue to scale down, especially by using a combination of reticle enhancement techniques (RET) with photomasks, including curved features."

The three top wafer foundries continue to use DUV and EUV, but everyone else has the opportunity to leverage the existing investment in 193nm processes. However, at the forefront of 193nm, fabs face many challenges in achieving sub-nano alignment accuracy, maximizing equipment utilization, and improving overall yield.

Siemens EDA Product Development Senior Director John Sturtevant said: "A lot of money can be made in the semiconductor field away from the cutting edge, and we tend to overlook this to some extent." "Very few companies focus on EUV, and ultimately High NA EUV, but there are many companies that have invested in 193nm and may invest in immersion in a few years. These companies have a lot of capabilities, and the question is how to make them push these resolutions as much as possible with the highest return."

Rayleigh Resolution Standard

In essence, the resolution of any lithography process is constrained by the Rayleigh resolution standard. This limit is determined by the wavelength, numerical aperture, and a coefficient called k1. Since the wavelength and numerical aperture are currently at their limits, k1 is the field where many innovative solutions are applied to improve resolution, reduce spacing, and achieve nodes as low as 20 nanometers. These smaller critical dimensions can be achieved by using a combination of smaller light wavelengths and larger lens numerical apertures (NA), while pushing k1 as close to the physical limit of 0.25 in lithography.

CD = k1 * λ / NA

In the Rayleigh equation, CD is the possible minimum feature size, λ is the wavelength of light, and NA is the numerical aperture of the lens on the scanner used. NA defines how much light passes through, and k1 is a coefficient composed of a variety of possible processes.Immersion Lithography

Immersion lithography is a technique that uses a liquid medium (usually water) between the projection lens and the wafer to increase the numerical aperture (NA), thereby enhancing the resolution of the lithography process. The liquid medium also increases the depth of focus, which helps to reduce the impact of wafer surface topography variations, enabling a larger process window and higher yield. The first practical application of immersion lithography in the semiconductor industry occurred around 2006, as a solution to push the limits of optical lithography to the limits achievable by dry lithography after the repeated delays in the introduction of EUV (Extreme Ultraviolet) technology.

Liquid immersion brings new challenges in fluid handling and contamination control. Specialized immersion systems have been developed to handle, distribute, and effectively recover the immersion fluid. Maintaining the cleanliness of the immersion liquid is crucial to avoid defects and yield issues in the lithography process.

Due to the presence of the immersion liquid, immersion lithography also imposes additional restrictions on mask design. The interaction between the immersion liquid and the mask can cause lens effects and alter image quality. Designing masks that can withstand fluid interactions and ensure accurate patterning has always been a significant challenge.

Multiple Patterning

Multiple patterning is a technique that involves breaking down complex patterns into multiple simpler patterns, then exposing these patterns separately on the wafer and combining them to form the desired pattern. This technique was initially explored as a complementary phase-shifting mask technique in the early 1990s, but its practicality in manufacturing was considered problematic. However, due to the continuous delays in EUV technology, the industry was eventually forced to adopt multiple patterning techniques in the mid-2000s to continue the progression of Moore's Law and facilitate the transition to advanced process nodes.

"As we cannot bypass the wavelength limit or the numerical aperture, we see an increasing number of companies investing in double patterning to achieve lower nodes from 45 nanometers to 28 nanometers and then to 22 nanometers," said Sturtevant. "Double patterning, as well as multiple patterning, is the ultimate trick to reduce the k1 factor of the Rayleigh criterion, because once you perform double patterning, you halve it."

In the past decade, a great deal of work has been done to develop effective algorithms to decompose the input design into two, three, or even four masks. Memory manufacturers particularly favor self-aligned double patterning (SADP) or self-aligned quadruple patterning (SAQP), leveraging the ingenuity of the process, including deposition and etching techniques.

"The current minimum resolution of the immersion 193 scanner is 1.35NA, which is 80nm, and double patterning can be reduced to a 40nm pitch (20nm lines x 20nm spaces)," said Phillipe Leray, Senior Director of Patterning at imec. "By dividing the pitch by a quarter, a basic rule of 20 to 21 nanometers can be achieved. The control of critical dimension uniformity is limited by the 'walking' phenomenon of the core structure's pitch, and the edge placement error of the block and via layers is a key limitation, but the industry has accumulated a wealth of experience. The level of control achieved today is mature and very competitive."

Technologies such as Self-Aligned Double Patterning (SADP), Self-Aligned Quadruple Patterning (SAQP), and Self-Aligned Litho-Etch-Litho-Etch (SALELE) are all multiple patterning solutions. These processes rely on spacer deposition techniques, mainly Atomic Layer Deposition (ALD), which can control the final critical dimensions (CD).Rethinking Masks

Curved masks offer an intriguing opportunity to improve Sub-Resolution Assist Features (SRAF) and expand the process window. Although SRAF technology has been in use since the i-line lithography era, advancements in depth of focus have highlighted the benefits of transitioning from straight-line (Manhattan) SRAF to curved SRAF.

"As long as the mask can be written accurately within a reasonable time/cost, curved masks can provide excellent wafer effects," says Fujimura. "Given the resist and writing method, multi-beam can write any shape in a constant time. Variable Shaped Beam (VSB) writing time is a function of the number of shots, but Mask-Wafer Co-Optimization (MWCO) combines overlapping VSB shots and produces superior wafer quality simulations with fewer shots by evaluating shot positions based on mask-wafer double-precision. Our recent results show that the number of shots is higher compared to traditional (non-curved) Optical Proximity Correction (OPC) with a process window that extends far beyond the wafer process window."

The transition to curved SRAF can enhance the process window by about 20%. While it is not a necessity for 193-nanometer and above technologies, it has proven valuable for smaller nodes. The availability of multi-beam mask writers has facilitated the adoption of curved masks, breaking the long-standing pattern of mask cost being tied to the number of shots. Although curved masks increase cost, they are relatively small compared to the investment in EUV lithography.

"As EUV begins to enter high-volume manufacturing (HVM), the industry starts to adopt multi-beam mask writers," says Fujimura. "Now almost all EUV masks are written with multi-beam mask writers, but the previous generation of Variable Shaped Beam (VSB) mask writers still dominates the mask writers offered by mask shops today."

However, it is not always as simple as it sounds. EDA tools are excellent at automating straight shapes but are far from it when it comes to curves. "It would be great if they really start incorporating curved features into the design," says Levinson of HJL. "That's the next step. There's a whole bunch of things there, such as how do you do layout routing? Once you do that, you have to deal with parasitic extraction."

OLE for Process Control

A key factor in achieving higher yields from extended 193nm technology is OLE for process control (OPC). Semiconductor factories use many devices from different manufacturers, each with its own communication protocol. OPC acts as a framework that enables seamless communication and integration between various software applications, equipment, and control systems involved in the manufacturing process.

OPC provides a standardized interface for integrating and optimizing equipment performance. By implementing OPC servers on equipment and OPC clients in control systems, manufacturers can collect real-time equipment data, perform equipment health monitoring, and implement predictive maintenance strategies. This integration and optimization help to improve yield by minimizing equipment downtime, reducing variability, and ensuring effective process control.OPC supports real-time process monitoring, enabling manufacturers to closely monitor key parameters and variables throughout the entire manufacturing process. In the advanced nodes of 193nm technology, precise control is essential, and OPC helps to collect and analyze data from multiple sources, such as sensors, actuators, and metrology equipment. This real-time monitoring helps to identify process deviations and take quick corrective actions, ultimately improving yield and reducing manufacturing defects.

As the industry pushes the frontier of 193nm lithography technology, OPC has become a standard practice. Companies at the forefront of technology have adopted OPC to overcome challenges associated with smaller nodes and 193-nanometer lithography.

The combination of OPC and reticle enhancement is a powerful approach to improve yield and accuracy by reducing edge placement errors to sub-nanometer tolerances. The accuracy of OPC simulation complements the need for in-line verification, which also drives the adoption of advanced metrology technologies.

Machine Learning

Semiconductor manufacturers are harnessing the power of machine learning (ML) and deep learning (DL), two subsets of artificial intelligence (AI), to tackle complex challenges and unlock new opportunities in their 193nm processes. ML algorithms analyze vast amounts of data generated during the lithography process, enabling faster and more accurate identification of key features and potential issues.

"The AI train never stops," said Sturtevant. "But fabs are still reluctant to put these multi-million-dollar reticle sets into AI because what if it does something strange in a certain design layer or somewhere in the circuit? So, the conclusion still exists, but there is a great opportunity for machine learning techniques to find patterning hotspots. If you can do this by improving efficiency through analysis, it's a multi-million-dollar savings proposal for the fab, otherwise, the fab has to use a lot of things, such as brightfield inspection metrology to find these in the process."

Pattern recognition algorithms trained on large datasets can quickly identify patterns and optimize exposure parameters, enabling higher resolution and better critical dimension (CD) control. Hotspot detection using ML algorithms helps identify areas prone to lithography process failures, allowing proactive measures to mitigate these issues. Additionally, ML-supported defect detection systems provide real-time analysis, reducing false positives and improving overall yield.

"Supporting ILT/OPC is one of the most prominent ways deep learning is used to help semiconductor manufacturing, but other areas such as automatic defect classification (ADC), machine maintenance prediction, or fault identification are also suitable for deep learning contributions," said Fujimura.

By analyzing the complex interactions between process inputs and outputs, ML models can determine the optimal process conditions to maximize yield and minimize defects. This optimization can improve process efficiency and product quality, especially as the industry explores new avenues such as small chips and 3D packaging.

In addition to pattern recognition and defect detection, ML plays a crucial role in data processing for various lithography applications. For example, ML can be used for defect classification, electron beam image denoising, and electrical performance prediction.Alternative Choices

Lithography is not the only method for manufacturing chips. Most lithography is used to etch lines into silicon or other materials. Some structures can also be grown uniformly using directed self-assembly, although it is currently more used for fixed patterns rather than printing them on masks or chips.

"There are several different ways to use DSA," said David Fried, Vice President of Lam Research's computational products. "There are pattern repair applications where you can still complete a full pattern module, but then you can use DSA to repair some pattern non-uniformities, such as missing hole defects or smoothing the roughness of line edges. I have seen some great demonstrations of DSA in these types of processes, and we will soon see the use of DSA in this way. DSA will not replace deposition and patterning processes, it just enhances them. Pattern multiplication is an interesting aspect of DSA, where you can pattern a single line and then let the DSA process generate a frequency-multiple version of that line. However, this is tricky. The industry has done so well in spacer-assisted multiple patterning that DSA will face a challenging time replacing spacer-assisted frequency multiplication. In addition, the actual pattern growth of DSA may still have a long way to go. These are three different potential insertion points for DSA. The first may happen soon. The second will be in trouble because the industry is already very good at spacer-assisted multiple patterning. I'm not sure if or when the third use case will happen."

Looking to the Future

Extending the 193nm process to smaller nodes will continue to play an important role in semiconductor manufacturing. Despite challenges and limitations, the industry has made significant progress in developing technologies such as multiple patterning to achieve spacing scaling. Continuous advancements in spacer deposition technology and lithography processes will further refine control of CDU and edge layout, enabling smaller spacing basic rules.

Moreover, the integration of small chips and 3D processes/packaging brings new opportunities and complexities. Collaboration between chip designers, lithography experts, and packaging engineers is crucial to ensure efficient integration while maintaining high reliability and performance.

Utilizing ML algorithms for data processing and optimization will improve the overall efficiency and effectiveness of the lithography process. As the semiconductor industry evolves, it will witness transformations driven by machine learning, advanced lithography technologies, and margin optimization strategies. The increasing complexity of designs, adoption of new materials, and demand for higher-performance devices all require the adoption of it.

"If you look at the roadmap for the next 8 to 10 years, we will eventually see the end of classical Moore's Law scaling, because the fact is, no one is working at wavelengths below 13.5 nanometers, and no one is really researching numerical apertures above 0.55," said Sturtevant. "After about 1.2 nanometers or 12 angstrom nodes, we will not have smaller spacings. So, the next question is, how will we achieve innovation? I think multiple patterning, curved masks, machine learning, and 3D integration are the main targets people point out to achieve more cost-effective manufacturing, enabling more functionality in each package. This will make most manufacturers not have to invest in the next generation of lithography equipment. By adopting these methods,

Extending the 193nm process to smaller nodes brings challenges and opportunities to the semiconductor industry. Despite difficulties in controlling CDU and edge placement, multiple patterning and spacer deposition technology have shown hope for achieving spacing scaling. Machine learning technology facilitates data processing in lithographic applications, optimizing decision-making and process parameters.

Nevertheless, to succeed at smaller nodes and innovative chip architectures, there is still a need for enhanced collaboration between experts in chip design, lithography, packaging, and AI/ML to ensure that 193-nanometer lithography technology remains compatible with emerging trends.