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For more than half a century, microelectronics technology has rapidly developed roughly in accordance with "Moore's Law." However, in recent years, with the evolution of chip manufacturing processes, the pace of iteration of "Moore's Law" has slowed down, leading to a sharp increase in the marginal cost of chip performance growth. According to statistics from IBS, after reaching the 28nm process node, if the process node continues to be reduced, the manufacturing cost per million transistors not only does not decrease but also increases.

On the other hand, while Moore's Law is slowing down, the demand for computing power is surging. With the rapid development of emerging fields such as cloud computing, big data, artificial intelligence, and autonomous driving, the requirements for the performance of computing chips are becoming higher and higher.

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In the post-Moore era, facing the bottleneck of computing demand, the physical limits of chip manufacturing, and the marginal increase in economic benefits, the semiconductor industry has begun to explore new development paths.

Among them, advanced packaging has become an important track beyond Moore's Law.

Advanced packaging plays a more important role in the process of improving chip integration, reducing chip distance, accelerating the speed of electrical connections between chips, and optimizing performance. It is becoming an important guarantee for the continuous improvement of system performance and meeting the needs of "light, thin, short, and small" and system integration.

It can be seen that with the increase in the demand for large computing power, and the increasing difficulty of advancing to more advanced processes for single chips, advanced packaging has become a key solution to reduce the cost of unit computing power.

The latest Advanced Packaging Market Monitor data from Yole Group shows that the global market size for advanced packaging will grow from $44.3 billion in 2022 to $78.6 billion in 2028, with a compound annual growth rate (CAGR) of 10.6%.

Under the market potential, front and back-end leading manufacturers are scrambling to seize the market, actively investing in advanced packaging technology.From the perspective of the dynamics of wafer foundries, during the sweet period when the foundry process developed rapidly in accordance with Moore's Law, packaging did not enter the field of vision of wafer foundries. However, in recent years, with the slowdown of Moore's Law and the rapid increase in the cost of advanced processes, the focus of some major wafer foundries has shifted from the pursuit of more advanced nanometer processes to the innovation of packaging technology. Chip manufacturers such as TSMC, Intel, Samsung, and UMC have all entered the packaging field, and advanced packaging technology has undoubtedly become an important battlefield for the competition among foundry giants.

Foundry giants are focusing on advanced packaging

TSMC's advantages are highlighted

More than 10 years ago, TSMC foresaw that with the rapid miniaturization of the front-end semiconductor process, the back-end packaging technology would not keep up with the pace of the front-end process. At that time, Moore's Law would really become ineffective. Therefore, it resolutely decided to invest in packaging technology and established the Integration of Interconnect and Packaging Department (IIPD) at the end of 2008.

In 2009, against the backdrop and impact of the financial crisis, TSMC fell into a predicament of operating losses and was forced to reduce salaries and lay off employees. At the same time, the development cost of the 28nm process technology segment increased rapidly; TSMC also faced strong challenges from Samsung, Intel, GlobalFoundries, and UMC.

Under internal and external troubles, Zhang Zhongmou made a comeback to take charge of TSMC, and also invited Jiang Shangyi, who had retired, to take the helm of R&D to develop advanced packaging technology for differentiated competition.

In the fall of 2011, Yu Zhenhua, the technical leader of CoWoS, brought the first product - CoWoS.

CoWoS (Chip On Wafer On Substrate) is a 2.5D integrated production technology, a combination of CoW and oS: first, the chip is connected to the silicon wafer through the Chip on Wafer (CoW) packaging process, and then the CoW chip is connected to the substrate, integrated into CoWoS. It is reported that this is also the concept proposed by Jiang Shangyi in 2006.

The core of CoWoS is to stack different chips on the same silicon interposer to achieve interconnection of multiple chips. In the silicon interposer, TSMC uses microbumps (µBmps), through-silicon vias (TSV) and other technologies, replacing the traditional wire bonding used for chip-to-chip connections, greatly increasing the interconnection density and data transfer bandwidth.The CoWoS technology has achieved the goals of improving system performance, reducing power consumption, and shrinking packaging size, thus also helping TSMC to maintain a leading position in subsequent packaging technologies and laying a solid foundation for transcending Moore's Law.

However, when CoWoS was first introduced, it was in an awkward situation. Due to its high price, TSMC's CoWoS packaging only received orders from the FPGA giant Xilinx. With CoWoS and the jointly developed TSV, μBump, and RDL technologies, four 28nm FPGA chips were successfully spliced together to launch the largest heterogeneous 3D IC Virtex-7 HT series FPGA chip in history, bringing significant advantages in chip size reduction, power consumption, and performance.

Although CoWoS can bring advantages to the finished chips, it was limited by cost, and only a few manufacturers' high-end products adopted it in the early stages of launch. Xilinx's project was the only order received by TSMC's advanced packaging project team in 2012. In response, TSMC decided to do "subtraction" for CoWoS and developed a low-cost version of CoWoS technology, namely InFO technology.

The reason why CoWoS technology is expensive is mainly due to the interconnection made in the middle of the silicon wafer. InFO packaging replaces the silicon interlayer with polyamide film material, thereby reducing the unit cost and packaging height. Both of these are important criteria for the success of InFO technology in mobile applications and the HPC market.

Therefore, InFO technology was widely praised as soon as it appeared. The processors of Apple's iPhone 7 and iPhone 7 Plus that year used InFO packaging technology. This also became a key factor for TSMC to monopolize the order of Apple's A-series processors later.

In fact, the product that really ignited CoWoS was the AI chip. In 2016, NVIDIA launched the first GPU chip using CoWoS packaging, GP100, which opened the prelude to the global AI boom; in 2017, Google and Intel products were successively subcontracted to TSMC, using CoWoS packaging. The CoWoS packaging and testing capacity, which had been sitting on the cold bench for many years due to high costs, was expanded for the first time in 2017.

In addition to CoWoS, TSMC also has other packaging technologies.

In April 2018, at the 24th Annual Technical Symposium in Santa Clara, California, TSMC announced the innovative System-on-Integrated-Circuit (SoIC) multi-chip 3D stacking technology to the outside world for the first time.

According to reports, SoIC is an innovative multi-chip stacking technology, a wafer-to-wafer bonding technology, and SoIC is a new generation of innovative packaging technology based on TSMC's CoWoS and multi-wafer stacking (WoW) packaging technology, which marks that TSMC has the capability to produce 3D ICs directly for customers.According to TSMC's official introduction, the SoIC service platform provides an innovative front-end 3D chip stacking technology, which is used to re-integrate small chips separated from the System on Chip (SoC). The final integrated chip outperforms the original SoC in terms of system performance, and it also offers flexibility in integrating other system functions. Compared to the 2.5D packaging scheme, SoIC has a higher bump density, faster transmission speed, and lower power consumption.

TSMC points out that the SoIC service platform can meet the growing computing, bandwidth, and latency requirements in cloud, network, and edge applications. It supports CoW (Chip on Wafer) and WoW (Wafer on Wafer) schemes, which provide excellent design flexibility when mixing and matching different chip functions, sizes, and technology nodes.

In 2020, TSMC announced the merger of its 2.5D and 3D packaging products into a comprehensive brand, 3DFabric, further integrating process technology and packaging technology to enhance competitiveness.

The 3DFabric platform consists of SoIC (System Integration Chip), InFO (Integrated Fan-Out Packaging Technology), and CoWoS (Chip on Wafer on Substrate), providing the most complete and versatile solutions in the industry for integrating logic chiplet technology, HBM (High Bandwidth Memory), and special process chips, enabling more innovative product designs.

As part of the 3D Fabric, TSMC categorizes the "CoWoS" packaging technology into three types based on different interposers:

CoWoS_S: It uses a silicon substrate as the interposer. This type is the first "CoWoS" technology developed in 2011, and in the past, "CoWoS" referred to advanced packaging technology with a silicon substrate as the interposer.

CoWoS_R: It uses a rerouting layer (RDL) as the interposer.

CoWoS_L: It uses chiplets and RDL as the interposer, combining the advantages of CoWoS-S and InFO technology, offering flexible integration.Through early technology accumulation and a large number of successful cases, TSMC's CoWoS packaging technology has now iterated to the fifth generation.   From the first generation in 2011 to the fourth generation in 2019, CoWoS_S technology has continuously expanded the interposer area, the number of transistors and the memory capacity. It is reported that the next generation (sixth generation) "CoWoS_S" is planned to be developed in 2023. The size of the Si interposer is larger and there are four masks. The corresponding HBM specification seems to be "HBM3". TSMC also announced the formation of an advanced packaging ecosystem "3DFabric Alliance" in November last year, including EDA, IP, DCA/VCA, memory, OSAT, substrate, and testing. The leading enterprises in seven links aim to standardize their own packaging technology in order to seize the dominant position in the future market in advance.   Semiconductor design companies such as NVIDIA, AMD, and AWS are using the 3DFabric Alliance. As the use of 2.5D and 3D packaging attracts more product ideas, the number of partners will increase over time, and 3D chip design will also be supported by the teamwork gathered in the 3DFabric Alliance. Although the current contribution of AI chip orders to TSMC is not high, the market demand continues to increase. In addition to orders from IC design giants such as NVIDIA, AMD, Broadcom, and Cisco, cloud service providers such as AWS and Google have also announced that they will invest in the development of AI chips, making TSMC's related production capacity, which currently covers almost all artificial intelligence manufacturing chip orders in the market, in short supply. With the full explosion of AI demand, TSMC has launched a large-scale expansion plan for CoWoS. It is reported in the industry that TSMC will once again place large orders to Taiwanese equipment manufacturers at the end of June, and also requires suppliers to fully shorten delivery time support. It is estimated that the monthly production capacity of CoWoS will reach 12,000 pieces by the end of this year, and will double in 2024. One of the reasons why TSMC entered the field of packaging and testing is that it hopes to extend its advanced process technology, by manufacturing high-end CPU, GPU, FPGA chips, and providing corresponding packaging and testing processes, to provide a complete "manufacturing + packaging and testing" solution. At present, TSMC's leading position in the field of advanced packaging is particularly prominent. It is understood that TSMC has achieved considerable revenue volume in advanced packaging, and its technology layout has also entered a critical node, and the scale of investment will continue to increase in the future. According to Yole data, from 2020 to 2022, TSMC's revenue scale in advanced packaging will increase from US$3.6 billion to US$5.3 billion, with a compound annual growth rate of 21.3%; capital expenditure on advanced packaging will increase from US$1.5 billion to US$4 billion, with a compound annual growth rate of 63.3%. In terms of market share, TSMC's revenue scale and capital expenditure on advanced packaging will rank third and second in the world in 2022, respectively.It is evident that TSMC always maintains a "two-pronged" approach in advanced packaging and advanced processes to ensure its dominant position in wafer foundry, sitting as firmly as Mount Tai.

Intel is in hot pursuit

As an IDM and a major wafer foundry, Intel is also actively deploying 2.5D/3D packaging.

Through years of technological exploration, it has successively launched various advanced packaging technologies such as EMIB, Foveros, and Co-EMIB, striving to achieve the goal of doubling interconnect bandwidth and halving power consumption through 2.5D, 3D, and embedded heterogeneous integration.

EMIB is Intel's attempt in 2.5D IC, and its full name is "Embedded Multi-Die Interconnect Bridge". Because it does not introduce an additional silicon interposer, but only adds a silicon bridge layer (Silicon Bridge) at the edge connection of the two bare dies, and re-customizes the I/O pins on the edge of the bare dies to match the bridge standard.

In December 2018, Intel demonstrated a new 3D packaging technology called "Foveros". This is another leap in Intel's advanced packaging technology following the breakthrough EMIB packaging technology launched by Intel in 2018.

According to reports, the Foveros technology is the first time Intel has introduced the advantages of 3D stacking, which can stack logic chips on logic chips, and interconnect between horizontal and vertical directions, further reducing the bump pitch to 50-25um. Foveros has paved the way for devices and systems that integrate high-performance, high-density, and low-power silicon process technologies.

Intel said that Foveros can integrate chips of different processes, structures, and purposes, thus assembling more computing circuits onto a single chip, achieving high performance, high density, and low power consumption. The technology provides great flexibility, allowing designers to "mix and match" different technological patent modules, various storage chips, I/O configurations in new product forms, and enabling products to be broken down into smaller "chip combinations".

At the SEMICON West conference held in 2019, Intel once again launched a new packaging technology called Co-EMIB, which is an innovative application that combines EMIB and Foveros technologies. It allows two or more Foveros components to be interconnected, and basically reaches the performance level of a single chip. Designers can also use Co-EMIB technology to achieve high bandwidth and low power consumption connections for simulators, memory, and other modules.At its 2020 Architecture Day, Intel showcased its new advancements in the field of 3D packaging technology, which it calls "Hybrid bonding" technology.

Most packaging technologies today use the traditional "thermal compression bonding" technique, and hybrid bonding is an alternative to this technology. This new technology can accelerate the achievement of a bump pitch of 10 microns and below, providing higher interconnect density, bandwidth, and lower power consumption.

From Intel's advanced packaging technology roadmap, it can be seen that its advanced packaging mainly focuses on three aspects: interconnect density, power efficiency, and scalability. Among them, Foveros and hybrid bonding technologies mainly focus on power efficiency and interconnect density, while Co-EMIB and ODI technologies reflect the characteristics of integrated scalability. From Foveros to hybrid bonding technology, Intel gradually achieves smaller bump pitches, enabling the system to have higher current load capacity and better thermal performance. In the future, Intel will continue to strive to maximize functionality per cubic millimeter.

In May of this year, Intel released a blueprint for advanced packaging technology, planning to transform traditional substrates into more advanced glass substrates.

Reports indicate that Intel's move is an attempt to switch materials to achieve high-performance semiconductors that surpass the limitations of existing plastic substrates.

With the popularization of 3D packaging, thickness has become a more concerned factor. The key to improving performance by vertically stacking semiconductors is to reduce the thickness of the substrate. Glass substrates have a flat surface and can be made very thin. Compared with ABF plastic, their thickness can be reduced by about half, and thinning can improve signal transmission speed and power efficiency.

Therefore, Intel is expected to improve the 3D packaging structure through glass substrates.

In addition, Intel is also advancing a technology that can shorten the contact distance between the chip and the circuit board (bump pitch). The shorter the contact distance, the smaller the packaging size, and thus the higher the performance. Intel has now achieved a bump pitch of about 36μm, and Intel has stated that it plans to reduce it to 25μm next year.From the above figure, it can also be seen that Intel is developing a hybrid bonding technology called Intel Foveros Direct. So far, solder balls have been used when stacking semiconductors or connecting them to circuit boards. Hybrid bonding, on the other hand, directly connects copper and copper with excellent electrical properties to reduce the stacking gap and improve signal transmission speed. Intel predicts that hybrid bonding will reduce the bump pitch to below 10μm, and will be applied to Intel's manufacturing process from the second half of this year at the earliest.

In addition, with the surge in computing demand triggered by ChatGPT, the CPO (Co-Packaged Optics) technology in silicon photonic modules, as a key technology to optimize computing power costs, has great development potential. Intel is also laying out in this area.

Co-packaged photonics is recognized by the industry as the future high-speed product form, and is one of the best solutions to solve the heat and power consumption problems of high-speed optoelectronics in the future, and is expected to become the main focus of industrial competition.

It is understood that CPO is a new type of optoelectronic integration technology, which packages optical devices such as lasers, modulators, and photoreceivers at the chip level, directly integrating with the internal circuits of the chip, and improving the performance and power efficiency of the communication system through optical interconnection.

Compared with traditional optical modules, CPO can reduce power consumption by about 50% at the same data transmission rate, effectively solving the problem of the difficulty in improving data transmission capacity due to energy consumption limitations in high-speed and high-density interconnection transmission scenarios. At the same time, compared with the traditional optoelectronic technology based on III-V materials, the silicon photonic technology mainly used by CPO has advantages in cost and size.

For a long time in the past, Intel's packaging technology was mainly used in its own products, and had a smaller impact on the market. With the introduction of Intel's IDM 2.0 development strategy, wafer foundry business has become an important transformation project for Intel. In addition to manufacturing for fabless semiconductor companies such as Qualcomm, its packaging technology is also an object that Intel is actively promoting. Intel stated that customers can choose to be manufactured by TSMC, GF, etc., and then use Intel technology for packaging and testing, this model will bring more flexible product manufacturing methods to customers.

Intel emphasized that it has already negotiated with customers under the top 10 global chip packaging factories, and has been favored by industry players such as Cisco and AWS.

Samsung is slightly lagging behind

Although Samsung took the lead in mass-producing 3-nanometer chips ahead of TSMC last year, TSMC's unparalleled packaging technology explains why global technology giants still rely on TSMC. At present, the large orders for AI and autonomous driving chips are all taken by TSMC, and the market share gap between Samsung and TSMC is getting bigger and bigger.

Facing the opportunities of the AI era, Samsung will naturally not give up easily.At the Samsung Foundry Forum held at the end of June, Siyoung Choi, head of Samsung's foundry business, first revealed that the 2nm process for high-performance computing needs will be mass-produced in 2026. He then announced the establishment of the "MDI (Multi-Die Integration) Alliance" with partners in the fields of memory, substrate packaging, and testing. This alliance aims to build an ecosystem for 2.5D and 3D heterogeneous integrated packaging technology. Based on the alliance and ecosystem cooperation, Samsung will provide one-stop services to downstream customers and develop customized packaging solutions to meet the needs of high-performance computing and automotive fields.

Before this, Samsung had already launched 2.5D and 3D packaging technologies such as I-Cube and X-Cube. The establishment of the alliance will enhance its industrial chain integration capabilities and one-stop and customized service capabilities.

For 2.5D packaging, Samsung's I-Cube packaging process can compete with TSMC's CoWoS packaging process. In terms of 3D IC technology, Samsung launched the X-Cube packaging in 2020, which physically stacks silicon wafers or chips together, with each wafer connected through silicon through-silicon vias (TSVs), minimizing interconnect length and reducing power consumption while increasing transmission speed.

From a product perspective, Samsung has indicated that it has stacked four SRAMs on a logic core computing chip using the X-Cube packaging technology and connected them with TSV technology. The X-Cube packaging technology has been applied to the 7nm EUV process and is being verified in the next-generation 5nm process. It will focus on application fields such as HPC, 5G, and AI in the future.

In addition, Samsung plans to mass-produce the X-Cube (u-Bump) packaging technology in 2024, which can handle more data than ordinary bumps, and is expected to launch a bumpless packaging technology that can handle more data than X-Cube (u-Bump) in 2026. It is reported that in 2021, Samsung also claimed to be developing "3.5D packaging" technology, but there has been no recent news.

At the 2023 "Samsung Foundry Forum," Choi Si-young, President of Samsung Electronics' foundry business, also introduced Samsung's foundry road map strategy. Choi Si-young said that Samsung plans to expand the application of chips manufactured with GAA process technology to 3D packaging by 2025. The reason is that process scaling has limitations in reducing costs and shrinking chip sizes, so Samsung is diversifying its advanced back-end technologies.

The industry has not yet combined GAA process technology with 3D advanced packaging technology, mainly because both process technologies are highly complex. Among them, GAA process technology replaces the traditional FinFET process technology, maximizing the area of the data transmission path while reducing the size of the chip. As for 3D advanced packaging, it is an integration technology that allows different small chips to be stacked together and function like a single chip within a single package.

These technologies are particularly important under the current situation where process scaling is gradually reaching its limits. Currently, competitors such as Intel and TSMC are fiercely competing in the field of advanced packaging to enhance the commercialization of these technologies.

Compared with TSMC and Intel, although Samsung Electronics' investment in advanced packaging is slightly slower, the bet on advanced packaging in the past two years has also been very large.In recent years, Samsung introduced Fan-Out Panel Level Package (FOPLP) technology, which further reduces the profile height of the package, enhances interconnection bandwidth, and compresses the cost per unit area on a large-area fan-out packaging. The aim is to achieve a higher cost-performance ratio.

Samsung's advanced packaging technology started relatively late compared to TSMC. Samsung originally intended to capture the mobile AP market share with FOPLP technology. However, Samsung has not been able to effectively solve the warping issues of FOPLP. At the same time, the chip precision of FOPLP packaging cannot be compared with wafer-level packaging, making it difficult to improve the yield and cost challenges. Currently, the chips mass-produced using FOPLP are still mainly used in smart wearable device applications, and they have not yet achieved mass production in higher-demand applications such as smartphones.

Since the beginning of this year, Samsung has been investing in its Cheonan packaging production line.

According to industry insiders, Samsung is also accelerating the layout of FO and plans to invest $75 million to establish a related production line in Japan. It is also seeking to strengthen ties with Japanese chip manufacturing equipment and material suppliers. In the FO field, TSMC currently dominates, accounting for about 77% of the market share, and Samsung intends to take a share of the market. According to Samsung's previously announced plan, its goal is to increase the advanced process capacity by more than three times compared to 2022 by 2027.

In addition to investment and layout in product innovation, Samsung Electronics also actively promoted packaging infrastructure construction and talent introduction last year. In December 2022, Samsung Electronics established an Advanced Packaging (AVP) department, responsible for packaging technology and product development, with the goal of transcending the limits of semiconductors with advanced packaging technology.

Kang Moon-soo, Vice President of Samsung AVP Business and team leader, recently pointed out that Samsung Electronics is the only company in the world engaged in memory, logic chip foundry, and packaging business. Therefore, leveraging these advantages, Samsung will provide competitive packaging products, connecting high-performance memory, such as through heterogeneous integration technology, and producing the most advanced logic semiconductors and HBM through EUV manufacturing technology.

"In the future, Samsung will focus on developing the next generation of 2.5D and 3D advanced packaging solutions based on Redistribution Layer (RDL), silicon interposer/bridge, and Through-Silicon Vias (TSV) stacking technology," Kang Moon-soo further emphasized.

To achieve breakthroughs and catch up in the field of advanced packaging, in March of this year, Samsung Electronics hired Lin Juncheng, a senior engineer who had worked at TSMC for nearly 19 years, as the Vice President of the Advanced Packaging Business Team (AVP) of the Semiconductor (DS) Department. Lin Juncheng is expected to carry out the development of advanced packaging technology in this department in the future.

Lin Juncheng worked at TSMC from 1999 to 2017 and is known as a "semiconductor packaging expert." During this period, he applied for more than 450 US patents, laying the foundation for TSMC's current pride in 3D packaging technology.Before hiring Lin Juncheng, Samsung Electronics also recruited Kim Woo-pyung, who was originally from Apple, and appointed him as the head of the U.S. Packaging Solutions Center.

With a strong layout in advanced packaging technology, coupled with an aggressive schedule for mass production in the 3nm and 2nm advanced process areas, Samsung is intensifying its competition with TSMC in the field of large AI chip orders. Regardless of whether Samsung can challenge TSMC's leading position in the AI era, as long as there is a sense of competition and action, it can gradually improve the cost-effectiveness of wafer-level packaging through more intense competition, giving chip design companies more choices.

UMC Quickly Follows Up

On June 26, wafer foundry UMC announced that it would acquire R&D production software from Siemens EDA for NT$385 million. It is expected to provide UMC with 3D IC planning and assembly verification solutions for wafer stacking (WoW) and chip-on-wafer (CoW) technology.

In other words, UMC will have the capabilities of 2.5D, 3D IC, and fan-out wafer-level packaging to meet customers' demand for advanced packaging.

Before this, there were also signs of UMC's layout in the field of advanced packaging. At the beginning of this year, UMC announced a joint development of 3D IC hybrid bonding (Hybrid Bond) solutions with Cadence, which UMC has also prepared, integrating cross-process technology to support the development of terminal applications such as edge AI, image processing, and wireless communication.

UMC customers' demand for high-performance computing, RF, and AIoT applications is increasing, and the demand for 3D IC is correspondingly increasing. Cooperating with global EDA factories can help customers accelerate the integration of product design and market launch time. With its rich experience in one-stop services such as wafer bumps, stacked chips, and wafer-level packaging, UMC expands to 2.5D, 3D IC solutions, striving to seize the business opportunities of advanced packaging.

GlobalFoundries Changes Course for Layout

In 2019, GlobalFoundries announced that it successfully taped out high-performance 3D packaging chips based on the ARM architecture using the 12nm FinFET process, which means that GlobalFoundries has also entered the field of 3D packaging.

GlobalFoundries announced in 2018 that it would give up further research and development in the direction of 7nm and more advanced manufacturing processes, but this does not mean that there will be no further action in other new technologies.The recent push in 3D packaging technology is precisely the effort made by GlobalFoundries under the big trend. Its newly developed 3D packaging solutions not only provide IC design companies with heterogeneous logic and logic/memory integration pathways, but also optimize the production node manufacturing, thereby achieving lower latency, higher bandwidth, and smaller feature sizes. This means competing with companies such as Intel and TSMC for the technological initiative in the era of heterogeneous computing.

GlobalFoundries Chief Technology Expert John Pellerin said, "In the era of big data and cognitive computing, the role of advanced packaging is far more than ever before. The use of AI and the demand for high-throughput energy-saving interconnects are driving the growth of accelerators through advanced packaging technology."

Earlier this year, GlobalFoundries officially announced on its website that it has formed a strategic partnership with Amkor Technology, the largest semiconductor packaging and testing service provider in the United States. GlobalFoundries plans to transfer its 12-inch wafer-level packaging production line from its Dresden factory to Amkor's factory in Porto, Portugal, to establish the first large-scale back-end facility in Europe.

The announcement stated that Amkor currently has the only large-scale OSAT facility in Europe, while GlobalFoundries is the largest and most advanced semiconductor manufacturing service company in Europe. This partnership creates more European supply chain autonomy for key end markets, including automotive, through an advanced packaging semiconductor supply chain outside of Asia.

Amkor Business Unit Executive Vice President Kevin Engel said, "The strategic cooperation with GlobalFoundries will strengthen the advanced semiconductor packaging supply chain in Europe, enhance competitiveness, and complement the existing capabilities in Asia. The cooperation between Amkor and GlobalFoundries allows us to significantly expand production scale and bring more assembly and testing capabilities to the market to support our European and global customers."

SMIC Joins Hands with Jiangsu Changjiang Electronics Technology

SMIC also sees the prospects of advanced packaging.

As early as 2014, SMIC and Jiangsu Changjiang Electronics Technology jointly established SMIC Changjiang, which is the world's first mid-silicon wafer manufacturing enterprise that uses the front-end integrated circuit chip manufacturing system and standards, and serves global customers with an independent professional foundry model.

Starting with advanced bumping and re-routing processes, SMIC Changjiang is committed to providing mid-silicon wafer manufacturing and testing services, and further developing advanced three-dimensional system integration chip businesses.It is understood that currently, SMIC's Jiangyin base provides 12-inch mid-process silicon wafer processing, focusing on 12-inch bumps and advanced wafer-level packaging; the Shanghai base provides 8-inch mid-process bumps and wafer-level packaging. In addition, both Jiangyin and Shanghai have testing factories, capable of providing test program development, probe card production, wafer testing, failure analysis, and failure testing services.

In conclusion, as computing requirements become increasingly complex, heterogeneous computing is gaining popularity, and more types of chips need to be integrated. Relying solely on the method of reducing line width can no longer meet the requirements for performance, power consumption, area, and signal transmission speed at the same time.

Under these circumstances, more and more semiconductor manufacturers are starting to focus on system integration. In addition to traditional outsourced packaging and testing manufacturers (OSATs), in recent years, wafer foundries and IDMs have also been vigorously developing advanced packaging or related technologies, and even Fabless and OEM companies are also participating, seeking solutions through packaging technology.

Enterprises with different business models are competing in the same high-end packaging market space. However, manufacturers with different business models also invest different resources in packaging business, and there are differences in technological development routes.

In terms of foundries, due to the continuation of front-end processes involved in 2.5D/3D packaging technology, wafer foundries have a deep understanding of the front-end process and have a more profound understanding of the overall wiring architecture, following the route of highly integrated chip manufacturing and packaging. Therefore, in terms of high-density advanced packaging, foundries have more advantages than traditional OSAT factories.

This has also made advanced packaging a key development technology for several major mainstream semiconductor wafer manufacturers in the industry. TSMC, Intel, and Samsung, as major players in the foundry industry, have successfully utilized the growth of the advanced packaging market to continuously improve their technological barriers.

In the post-Moore era, advanced packaging is becoming a focus and inevitable choice for major manufacturers. In addition to the original IDM packaging and testing departments and OSAT outsourced packaging and testing companies, semiconductor manufacturing leaders have also shifted from the advancement of the past wafer manufacturing technology nodes to the innovation of advanced packaging technology.

TSMC, Intel, and Samsung, as leading players, have all taken out their "killer" moves to compete for industry status, and wafer foundries are becoming the biggest disruptors in this round of technological innovation.