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Wafer bonding is an emerging semiconductor processing technology that has rapidly developed over the past decade and has important applications in the fields of MEMS, CIS, and storage chips, attracting more and more attention.

In the ocean of information, the presence of wafer bonding is relatively thin compared to lithography technology. However, when we take out a mobile phone, its image sensor, accelerometer, microphone, 4G and 5G RF front-end, and some NAND, all apply wafer bonding technology to varying degrees. It can be said that wafer bonding technology has made an important contribution to our information-based life.

Wafer bonding (wafer bonding) can be distinguished from wire bonding and die bonding used in traditional packaging from its name. In Japanese, bonding is translated as "joining," which is more intuitively understandable for this process and process.

From the perspective of bonding methods, wafer bonding can be divided into permanent bonding and temporary bonding. The difference is also self-explanatory, permanent bonding does not need to be debonded after bonding, while temporary bonding still needs to be debonded to open the bonded wafers again.

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In terms of interface materials, it is divided into adhesive bonding with an intermediate layer, eutectic bonding, metal hot pressing bonding, fusion bonding without an intermediate layer, and anodic bonding.

The purpose of bonding is also different, such as providing airtight protection for devices, certain application scenarios in MEMS and SAW; for example, providing mechanical support for thinning wafers or layer transfer, such as the application in IGBT and BSI is based on this purpose; the latest and most important application is still the three-dimensional interconnection of transistors, HBM, 3D NAND, and the complementary field-effect transistor CFET and the back-end power supply network BPN under development, and the hybrid bonding that has emerged in recent years is a process that focuses on this application, named for its characteristics of both fusion bonding and metal bonding.

The early wafer bonding did not have high requirements for overlay accuracy control, and it was acceptable within 10 micrometers after bonding. However, since the beginning of BSI, the overlay accuracy requirement has reached the level of 1.5 micrometers, and for the application of 3D NAND and high-end BSI, it has reached below 300 nanometers or even 150 nanometers! With the development of bonding technology and its penetration into the front-end process, the author boldly speculates that the future may reach the requirement of tens of nanometers overlay accuracy.

Old wine in new bottles

As previously mentioned, the essence of bonding is joining, which uses various different physical and chemical methods to join two interfaces. The principle was discovered and applied long before humans cut the first wafer. Whether it is adhesive bonding with polymer compounds, eutectic bonding using welding principles, or fusion bonding attracted by van der Waals forces between ultra-smooth surfaces, the basic principle was already known before the birth of wafer bonding. However, the true large-scale industrial application of wafer bonding has only started in the last decade or so.In 1969, Wallis and Pomerantz first described the process of bonding silicon and soda-lime glass wafers together using an electric field at 500°C, which is known today as anodic bonding.

In 1986, IBM and Toshiba discovered fusion bonding during their research. After silicon wafers were mirror-polished, they could be bonded together through van der Waals forces at room temperature without the need for other adhesives, marking the beginning of direct silicon-silicon bonding. In the following years, fusion bonding techniques for SOI, MEMS, and III-V compound semiconductors were published. After the 1990s, room temperature bonding with plasma treatment of wafer surfaces, followed by low-temperature annealing, and fusion bonding without annealing under high vacuum were also developed.

In 2016, Sony first used copper-silica hybrid bonding to produce image sensors. This idea, which originated in the mid-1980s, finally became a reality after more than a decade of research and was accepted by the industry.

There are many ways to achieve three-dimensional interconnection through wafer bonding, but as shown in the above figure (a), the fusion bonding scheme and the hybrid bonding scheme (d) are more suitable for advanced CMOS processes.

Metal hot pressing bonding (c) requires extremely high pressure (10-100kN), and even anodic bonding may use high-voltage electric fields, which are not very compatible with CMOS processes and can easily damage the previous metal patterns. Therefore, the fusion bonding and hybrid bonding (d) that only require room temperature bonding and low-temperature annealing have gained more and more favor due to their good compatibility with CMOS processes.

Fusion bonding was not always so gentle. It evolved from the early process conditions that required high temperatures of 1000°C for several hours of annealing to only requiring plasma surface activation at room temperature, followed by bonding, and then annealing at temperatures below 400°C, or even without annealing under ultra-high vacuum after plasma surface activation, providing a strong guarantee for its CMOS process compatibility. The hybrid bonding that directly uses copper contacts for interconnection without TSVs has shortened the interconnection distance between the upper and lower wafers to the shortest, further improving electrical performance.

It is precisely because of the rapid development of fusion bonding and hybrid bonding that the biggest obstacle to wafer bonding moving towards CMOS interconnection processes has been removed.

Fusion bonding: from SOI to BSI

Fusion bonding is usually a process that bonds silicon-silicon or silicon-silica as the bonding interface after appropriate surface treatment. I have seen a saying that as long as the surface is smooth and flat enough, everything can be bonded, so special substrates like indium phosphide and lithium niobate can also be fused bonded with silicon wafers!The early and relatively well-known application of fusion bonding is in the production of SOI (Silicon on Insulator), a substrate material rich in optical and electrical properties. The preparation of SOI is naturally more complex than that of conventional silicon wafers. The early main method of preparing SOI wafers was through the fusion bonding of bare silicon wafers and thermal oxide wafers, followed by back thinning. However, due to its high cost, slow production speed, and poor uniformity, its application scenarios were relatively limited. Later, the SmartCut® technology developed by the French company Soitec made a leap in cost, production speed, and uniformity indicators. The bare silicon wafer, as a donor wafer, is fused and then automatically fractures after hydrogen ion implantation, separating the donor wafer, which can be reused after surface polishing.

Fusion bonding is more widely known for its use in the production of BSI (Back-Side Illumination) image sensors. In the early stages of BSI, the mechanical support of the patternless wafer was fused with the CMOS wafer, and the back of the CMOS was thinned to create a pixel array. With the development of the demand for image signal processing, a new method of face-to-face fusion bonding between the logic wafer for image processing and the CMOS wafer, interconnected by TSV (Through-Silicon Vias), has emerged. When the technology of hybrid bonding matures, BSI has also entered the era of high-density interconnection, which is a story for later.

In addition, the author has also seen cases in some papers where fusion bonding is used to interconnect chips such as micro-LEDs and MEMS with CMOS. Including in the CFET (Complementary FET) technology route of IMEC, there is also an application of using fusion bonding to make three-dimensional transistors. With the arrival of the three-dimensional era of semiconductors, the potential of fusion bonding is immeasurable.

Hybrid bonding: a business card of the new era.

Speaking of the most typical application of hybrid bonding, there is no doubt that it is the Xtacking® of Yangtze Memory. By different processes, the Memory wafer and the CMOS wafer are made in sequence, and the contacts between the two are built in the back-end process. Through hybrid bonding, these contacts are linked and connected, and Memory and CMOS are interconnected in the vertical direction.

According to the Fraunhofer Institute, there are three advantages of hybrid bonding:

Shorter interconnect distance: Not only is it not necessary to connect each other with wires, but it is also not necessary to use TSV to penetrate the entire CMOS layer. Interconnection can be achieved simply by connecting the copper contacts in the back-end process.Higher Interconnection Density: The area of copper contacts is extremely small, compared to the tin balls with a diameter of hundreds of micrometers and TSVs, the pitch size of copper contacts in the hybrid bonding process is even less than 10 micrometers, which undoubtedly can achieve a higher interconnection density.

Lower Cost: Undoubtedly, interconnecting each DIE separately requires more time, and wafer bonding can achieve large-area high-density interconnection, which contributes to a leap in production capacity! Naturally, production costs can also be reduced.

In addition to the previously mentioned BSI, there are also cases of hybrid bonding with micro-LEDs and CMOS. In the latest research, there are even practices of making micro-LEDs on small-sized wafers, cutting them into independent DIEs, and then re-bonding them onto a 12-inch wafer for hybrid bonding interconnection with a CMOS 12-inch wafer, which shows that its process compatibility is excellent. This is another advantage of hybrid bonding, where different technology nodes of CMOS can also be interconnected through copper contacts, and the flexibility of process selection has also been greatly improved!

Of course, hybrid bonding is not perfect, for example, it is impossible to know the failed DIE from the initial stage, and only after the integration, thinning, dicing, and testing can it be identified, which will greatly affect the yield of finished DIEs. Secondly, the bonding interface requires ultra-high flatness, and the internal stress of the wafer also needs to be controlled to reduce wafer warpage, all of which put forward stringent requirements for the control of subsequent processes. Compared with traditional packaging technology, the cleanliness level required for hybrid bonding, ISO3 or above, is much higher than the ISO5 cleanliness level required by traditional packaging and testing factories, which puts forward high requirements for the control of factory affairs and the environment.

The implementation of the process relies on the support of materials and equipment. Although it is a post-process, there are very few players involved. Among them, Suss from Germany and EVG from Austria are leading, and although Canon and Mitsubishi from Japan also have special bonding equipment, neither the market share nor the technical level can be compared with these two top players. The only systematic introduction of wafer bonding in China is the "Wafer Bonding Manual," in which the equipment of Suss and EVG has a very high appearance rate and is repeatedly mentioned, and their reputation and leading position are self-evident.

The product lines of Suss and EVG have a high degree of overlap, and both sides have covered all types of bonding processes almost at the same time, including not only bonding machines but also alignment machines for wafer alignment and double-sided lithography machines, and measurement machines for detecting bonding accuracy are also involved, but each has its own strengths. In the domestic bonding machine market, compared with EVG, Suss has a better reputation and market share in universities and research institutes, but EVG is better in industrial applications. Especially in the domestic advanced BSI production line, EVG's fully automatic fusion bonding machine GeminiFB has almost reached a market share of 100%!

At present, domestic bonding machines are still mainly low-end, although the bonding machines developed and produced by Shanghai S Company have penetrated the market of adhesive bonding and metal bonding, they have not yet entered the main position of fusion bonding. Another domestic company focusing on bonding machines is H Company, which, like S Company, is known for its lithography subsystem, and its 200nm alignment accuracy is still not comparable to the previous generation of EVG products, but it is also a major breakthrough for domestic enterprises! In addition, there are several semiconductor equipment manufacturing companies developing new bonding equipment, after all, up to last year, the growth of the CIS industry has continued for 10 years, and the market space is quite broad! Although the CIS market in 2022 has seen its first decline in 10 years, with the increasing demand for security and smart cities, the CIS market is large enough to accommodate players other than Suss and EVG.

In conclusion, over the past decade, the pace of advancing Moore's Law has gradually slowed down, and more and more semiconductor companies are seeking advanced packaging to drive the improvement of chip performance, and heterogeneous integration is one of the solutions, and wafer bonding technology provides an efficient implementation path, becoming a strong candidate process!When Intel and IMEC announced the future development roadmap of transistors in 2022, and after the 1nm era enters the CFET era, the author firmly believes that melt bonding and hybrid bonding will move from the back-end to the front-end, leading the way for the semiconductor industry's development over the next 15 years, along with high NA and hyper NA EUV lithography machines!